In the rapid development of computers many advancements have been seen in the areas of processor speed, throughput, communications, and fault tolerance. Microprocessor speed may be measured in cycles per second or hertz. Today's high-end 32-bit microprocessors operate at over 1.8 Ghz (gigahertz), 1.8 billion cycles per second, and in the near future this is expected to go substantially higher to 2.6 and 3.3 Ghz and beyond. At this sort of cycle speed a clock may have to generate a pulse or cycle at least ten times each billionth of a second and usually significantly faster.
With processors operating at such higher rates it is necessary to supply data to the processor when required from memory at a comparable rate otherwise a bottle neck is formed and the processor spends much of its time waiting for data. To improve the transfer rate of memory, Double Data Rate (DDR) memory transfer data at both the leading edge of a clock cycle and the trailing edge of the clock cycle. These memory have a source-synchronous clocking protocol to transfer data from the memory to the memory controller. Data (DQ) from memory is captured by the memory controller using a clock or strobe signal (DQS) supplied by the memory, However, in order to avoid data errors which may occur when the strobe signal levels change, each strobe signal from memory may be delayed, so that data may be strobed in the center of the valid data window. The precision of the delay is important because any variation in the delay translates into added setup/hold time for the memory controller. If the setup/hold time is too large, the system becomes unworkable. This is especially true as memory moves to faster speeds.